View AK4388A_4367206.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

[AK4388A] ms1008-e-02 2010/09 - 1 - general description the AK4388A offers the perfect mix for cost and per formance based audio systems. using akm's multi bit architecture for its modulator, the AK4388A deliver s a wide dynamic range while preserving linearity for improved thd+n performance. the ak 4388a integrates a combination of scf and ctf filters increasing performance for systems with exce ssive clock jitter. the 24 bit word length and 192khz sampling rate make this part ideal for a wide range of applications including dvd-audio. the AK4388A is offered in a space saving 16pin tssop package. features ? sampling rate ranges from 8khz to 192khz ? 128 times oversampling (normal speed mode) ? 64 times oversampling (double speed mode) ? 32 times oversampling (quad speed mode) ? 24-bit 8 times fir digital filter ? scf with high tolerance to clock jitter ? single ended output buffer ? digital de-emphasis ? soft mute ? i/f format: 24-bit msb justified, 24/16-bit lsb justified or i 2 s ? master clock: 256fs, 384fs, 512fs, 768fs or 1152fs (normal speed mode) 256fs or 384fs (double speed mode) 128fs, 192fs (quad speed mode) ? thd+n: -90db ? dynamic range: 106db ? power supply: 4.5 to 5.5v ? very small package: 16pin tssop (6.4mm x 5.0mm) ? ak4384 parallel mode compatible lrck bick sdti audio data interface mclk rstn ? modulator aoutl 8x interpolator scf lpf aout r v dd v ss v com de-emphasis control control port clock divider smute acks dif0 ? modulator 8x interpolator scf lpf dzf dif1 dem 192khz 24-bit 2ch ? dac AK4388A
[AK4388A] ms1008-e-02 2010/09 - 2 - ordering guide AK4388Aet -20 c +85 c 16pin tssop (0.65mm pitch) akd4388a evaluation board for the AK4388A pin layout 1 mclk lrck bick smute acks dif0 top view 2 3 4 5 6 7 8 dzf dem vss vdd vcom a outl a outr dif1 16 15 14 13 12 11 10 9 rstn sdti compatibility with ak4384, ak4388 1. function functions ak4384 ak4388 AK4388A thd+n -94db -90db ? output voltage 3.4vpp 3.2vpp ? slow roll-off filter available not available ? mode setting serial/parallel parallel ? dem in parallel control not available available ? audio format in parallel control 24-bit i 2 s 24-bit msb justified 24/16-bit i 2 s 24-bit msb justified 24/16-bit lsb justified ? zero data detect pin 2 pins 1 pin ? mclk, lrck, bick clock stop (rstn pin= ?h?) not available not available available 2. pin configuration ak4388/a ak4384 pin# pin# ak4384 ak4388/a mclk mclk 1 16 dzfl dzf bick bick 2 15 dzfr dem (pd) sdti sdti 3 14 vdd vdd lrck lrck 4 13 vss vss rstn pdn 5 12 vcom vcom smute smute/csn 6 11 aoutl aoutl acks acks/cclk 7 10 aoutr aoutr dif0 dif0/cdti 8 9 p/s (pu) dif1 (pu) : deference between ak4384 * pu: pull-up, pd: pull-down
[AK4388A] ms1008-e-02 2010/09 - 3 - pin/function no. pin name i/o function 1 mclk i master clock input pin an external ttl clock mu st be input on this pin. 2 bick i audio serial data clock pin 3 sdti i audio serial data input pin 4 lrck i l/r clock pin 5 rstn i reset mode pin when at ?l?, the AK4388A is in power-down mode and is held in reset. the AK4388A must always be reset upon power-up. 6 smute i soft mute pin ?h?: enable, ?l?: disable 7 acks i auto setting mode pin ?l?: manual setting mode, ?h?: auto setting mode 8 dif0 i audio data interface format pin 9 dif1 i audio data interface fo rmat pin (internal pull-up pin) 10 aoutr o rch analog output pin 11 aoutl o lch analog output pin 12 vcom o common voltage pin, vdd/2 normally connected to vss with a 10 f electrolytic cap. 13 vss - ground pin 14 vdd - power supply pin 4.5v~5.5v 15 dem i de-emphasis mode pin (internal pull-down pin) when at ?h?, the de-emphasis filter is available. 16 dzf o zero input detect pin note: all input pins except pull-up and pull-down pins must not be left floating. absolute maximum ratings (vss=0v; note 1 ) parameter symbol min max units power supply vdd -0.3 6.0 v input current (any pins except for supplies) iin - 10 ma input voltage vind -0.3 vdd+0.3 v ambient operating temperature ta -20 85 c storage temperature tstg -65 150 c note 1. all voltages with respect to ground. warning: operation at or beyond these limits may results in permanent damage to the device. normal operation is not guara nteed at these extremes. recommended operating conditions (vss=0v; note 1 ) parameter symbol min typ max units power supply vdd 4.5 5.0 5.5 v *akm assumes no responsibility for the usage beyond the conditions in this datasheet.
[AK4388A] ms1008-e-02 2010/09 - 4 - analog characteristics (ta = 25 c; vdd = 5.0v; fs = 44.1khz; bick = 64fs; signal frequency = 1khz; 24bit input data; measurement frequency = 20hz 20khz; r l 5k ; unless otherwise specified) parameter min typ max units resolution 24 bits dynamic characteristics ( note 2 ) fs=44.1khz bw=20khz 0dbfs ?60dbfs ?90 ?42 ?80 - db db fs=96khz bw=40khz 0dbfs ?60dbfs ?90 ?39 - - db db thd+n fs=192khz bw=40khz 0dbfs ?60dbfs ?85 ?39 - - db db dynamic range (-60dbfs with a-weighted) ( note 3 ) 98 106 db s/n (a-weighted) ( note 4 ) 98 106 db interchannel isolation (1khz) 90 100 db interchannel gain mismatch 0.2 0.5 db dc accuracy gain drift 100 - ppm/ c output voltage ( note 5 ) 2.95 3.20 3.45 vpp load resistance ( note 6 ) 5 k load capacitance 25 pf power supplies power supply current (vdd) normal operation (rstn pin = ?h?, fs 96khz) normal operation (rstn pin = ?h?, fs = 192khz) power-down mode (rstn pin = ?l?) ( note 7) 16 18 60 - 27 160 ma ma a note 2. measured by audio precision (system two). refer to the evaluation board manual. note 3. 100db at 16bit data. note 4. s/n does not depend on input bit length. note 5. full-scale voltage (0db). output voltage scal es with the voltage of vdd, aout (typ.@0db) = 3.20vpp vdd/5. note 6. for ac-load. note 7. the dif1 pin is held to vdd and the other all digital inputs including clock pins (mclk, bick and lrck) are held to vss.
[AK4388A] ms1008-e-02 2010/09 - 5 - filter characteristics (ta = 25 c; vdd = 4.5 5.5v; fs = 44.1khz) parameter symbol min typ max units digital filter (dem = off) passband 0.05db ( note 8 ) ?6.0db pb 0 - 22.05 20.0 - khz khz stopband ( note 8 ) sb 24.1 khz passband ripple pr 0.02 db stopband attenuation sa 54 db group delay ( note 9 ) gd - 19.3 - 1/fs de-emphasis filter (dem = on) de-emphasis error (dc referenced) fs = 32khz fs = 44.1khz fs = 48khz - - - - - - ?1.5/0 ?0.2/+0.2 0/+0.6 db db db digital filter + lpf (dem = off) frequency response 20.0khz 40.0khz 80.0khz fs=44.1khz fs=96khz fs=192khz fr fr fr - - - 0.2 0.3 +0.1/-0.6 - - - db db db note 8. the passband and stopband frequencies scale with fs(system sampling rate). for example, pb=0.4535fs (@ 0.05db), sb=0.546fs. note 9. calculated delay time caused by digital filter. this time is measured from setting the 16/24bit data of both channels to input register to the output of the analog signal.
[AK4388A] ms1008-e-02 2010/09 - 6 - dc characteristics (ta = 25 c; vdd = 4.5 5.5v) parameter symbol min typ max units high-level input voltage low-level input voltage vih vil 2.2 - - - - 0.8 v v high-level output voltage (iout = ?80a) low-level output voltage (iout = 80a) voh vol vdd-0.4 - - - 0.4 v v input leakage current ( note 10 ) iin - - 10 a note 10. except for the dif1 and dem pins. the dif1 pin has internal pull-up resistor, the dem pin has internal pull-down resistor, nominally 100k . (typ. 100k ) switching characteristics (ta = 25 c; vdd = 4.5 5.5v; c l = 20pf) parameter symbol min typ max units master clock frequency duty cycle fclk dclk 2.048 40 11.2896 36.864 60 mhz % lrck frequency normal speed mode double speed mode quad speed mode duty cycle fsn fsd fsq duty 8 32 120 45 48 96 192 55 khz khz khz % audio interface timing bick period normal speed mode double/quad speed mode bick pulse width low pulse width high bick ? ? to lrck edge ( note 11 ) lrck edge to bick ? ? ( note 11 ) sdti hold time sdti setup time tbck tbck tbckl tbckh tblr tlrb tsdh tsds 1/128fs 1/64fs 30 30 20 20 20 20 ns ns ns ns ns ns ns ns reset timing rstn pulse width ( note 12 ) trst 150 ns note 11. bick rising edge must not occur at the same time as lrck edge. note 12. the AK4388A can be reset by bringing rstn pin = ?l? ?h?.
[AK4388A] ms1008-e-02 2010/09 - 7 - timing diagram 1/fclk tclkl vih tclkh mclk vil dclk=tclkh x fclk, tclkl x fclk 1/fs vih lrck vil tbck tbckl vih tbckh bick vil figure 1. clock timing tlrb lrck vih bick vil tsds vih sdti vil tsdh vih vil tblr figure 2. serial interface timing trst vil rstn figure 3. power-down timing
[AK4388A] ms1008-e-02 2010/09 - 8 - operation overview system clock the external clocks, which are required to operate the AK4388A, are mclk, lrck and bick. the master clock (mclk) should be synchronized with lrck but the phase is not critical. the mc lk is used to operate the digital interpolation filter and the delta-sigma modulator. there are two methods to set mclk frequency. in manual setting mode (acks pin = ?l?, normal speed mode), the frequency of mclk is set automatically ( table 1 ). in auto setting mode (acks pin = ?h?), as mclk fre quency is detected automatically ( table 2 ), and the internal master clock becomes the appropriate frequency ( table 3 ). lrck mclk bick fs 256fs 384fs 512fs 768fs 1152fs 64fs 32.0khz 8.1920mhz 12.2880mhz 16.3840mhz 24.5760mhz 36.8640mhz 2.0480mhz 44.1khz 11.2896mhz 16.9344mhz 22.5792mhz 33.8688mhz n/a 2.8224mhz 48.0khz 12.2880mhz 18.4320mhz 24.5760mhz 36.8640mhz n/a 3.0720mhz table 1. system clock example (manual setting mode, acks pin = ?l?, normal speed mode) mclk mode sampling rate 1152fs normal 8khz~32khz 512fs 768fs normal 8khz~48khz 256fs 384fs double 32khz~96khz 128fs 192fs quad 120khz~192khz table 2. sampling speed (auto setting mode, acks pin = ?h?) lrck mclk (mhz) fs 128fs 192fs 256fs 384fs 512fs 768fs 1152fs 32.0khz - - 8.1920 12.2880 16.3840 24.5760 36.8640 44.1khz - - 11.2896 16.9344 22.5792 33.8688 - 48.0khz - - 12.2880 18.4320 24.5760 36.8640 - 88.2khz - - 22.5792 33.8688 - - - 96.0khz - - 24.5760 36.8640 - - - 176.4khz 22.5792 33.8688 - - - - - 192.0khz 24.5760 36.8640 - - - - - table 3. system clock example (auto setting mode, acks pin = ?h?) when mclk= 256fs/384fs, the auto setting m ode supports sampling rate of 32khz~96khz ( table 2 ). when the sampling rate is 32khz~48khz, dr and s/n will degrade by approximately 3db as compared to when mclk= 512fs/768fs. acks pin mclk dr,s/n l 256fs/384fs/512fs/768fs 106db h 256fs/384fs 103db h 512fs/768fs 106db table 4. relationship between mclk frequency and dr, s/n (fs= 44.1khz)
[AK4388A] ms1008-e-02 2010/09 - 9 - audio serial interface format data is shifted in via the sdti pin using bick and lrck inputs. the dif0-1 as shown in table 5 can select four serial data modes. the dif1 pin is internal pull-up pin. in all modes the serial data is msb-first, 2?s compliment format and is latched on the rising edge of bick. mode dif1 dif0 sdti format bick figure 0 l l 16bit lsb justified 32fs figure 4 1 l h 24bit lsb justified 48fs figure 5 2 h l 24bit msb justified 48fs figure 6 3 h h 16/24bit i 2 s compatible 48fs or 32fs figure 7 table 5. audio data formats sdti bick lrck sd t i 15 14 6 5 4 bick 0 1 10 11 12 13 14 15 0 1 10 11 12 13 14 15 0 1 3210 1514 ( 32fs ) ( 64fs ) 0 14 1 15 16 17 31 0 1 14 15 16 17 31 0 1 15 14 0 15 14 0 mode 0 don?t care don?t care 15:msb, 0:lsb mode 0 15 14 6 5 4 3 2 1 0 lch data rch data figure 4. mode 0 timing sdti lrck bick ( 64fs ) 0 9 1 10 11 12 31 0 1 9 10 11 12 31 0 1 19 0 19 0 mode 1 don?t care don?t care 23:msb, 0:lsb lch data rch data 88 20 22 21 23 20 22 21 23 figure 5. mode 1 timing
[AK4388A] ms1008-e-02 2010/09 - 10 - lrck bick ( 64fs ) sdti 0 22 1 2 24 31 0 1 31 0 1 23:msb, 0:lsb 22 1 0 don?t care 23 lch data rch data 23 30 22 2 24 23 30 22 1 0 don?t care 23 22 23 mode 2 figure 6. mode 2 timing lrck bick ( 64fs ) sdti 0 3 1 2 24 31 0 1 31 0 1 23:msb, 0:lsb 22 1 0 don?t care 23 lch data rch data 23 25 3 224 23 25 22 1 0 don?t care 23 23 mode 3 figure 7. mode 3 timing de-emphasis filte r a digital de-emphasis filter is built-in (tc = 50/15s). the dem pin is internal pull-down pin. the digital de-emphasis filter is enabled by setting the dem pin to ?h?. refer to ?filter characteristics? rega rding the gain error when the de-emphasis filter is enabled. in case of doubl e speed mode (mclk=256fs/384fs) and quad speed mode (mclk=128fs/192fs), the digital de-e mphasis filter is always off. dem pin de-emphasis filter 1 on 0 off (default) table 6. de-emphasis filter control (normal speed mode)
[AK4388A] ms1008-e-02 2010/09 - 11 - zero detection when the input data at both channels are continuously zeros for 8192 lrck cycles, the dzf pin goes to ?h?. the dzf pin immediately returns to ?l? if input data of both channels are not zero ( figure 8 ). soft mute operation soft mute operation is performed at digital domain. when the smute pin goes to ?h?, the output signal is attenuated by - in 1024 lrck cycles. when the smute pin is returned to ?l?, the mute is cancelled and the output attenuation gradually changes to 0db in 1024 lrck cycles. if the soft mute is cancelled within the 1024 lrck cycles, the attenuation is discontinued and returned to 0db in the same cycle. the soft mute is effective for changing the signal source without stopping the signal transmission. smute pin a ttenuation dzf pin 1024/fs 0db - a out 1024/fs 8192/fs gd gd (1) (2) (3) (4) notes: (1) 1024lrck cycles (1024/fs) at input data is attenuated to - . (2) the analog output corresponding to the digital input has group delay, gd. (3) if the soft mute is cancelled before attenuating to - , the attenuation is discontinued and returned to att level by the same cycle. (4) when the input data at both channels are continuously zeros for 8192 lrck cycles, the dzf pin goes to ?h?. the dzf pin immediately returns to ?l? if input data are not zero. figure 8. soft mute and zero detection
[AK4388A] ms1008-e-02 2010/09 - 12 - system reset the AK4388A must be reset once by bringing the rstn pin = ?l? upon power-up. the AK4388A is powered up and the internal timing starts clocking by lrck ? ? after exiting reset by mclk. the AK4388A is in reset state until lrck is input. power on/off timing the AK4388A is placed in the power-down mode by bringing the rstn pin ?l? and the registers are initialized. the analog outputs go to vcom (vdd/2). since click noise occurs at the edge of the rstn signal, the analog output should be muted externally if click noise aversely affects system application. rstn pin power reset normal operation dac in (digital) dac out (analog) external mute mute on (4) dzf ?0?data gd (1) (3) (5) gd (3) mute on ?0?data internal state (2) (2) notes: (1) the analog output corresponding to digital input has the group delay (gd). (2) analog outputs are vcom ( vdd/2) in power-down mode. (3) click noise occurs at the edge of rstn signal. this noise is output even if ?0? data is input. (4) mute the analog output externally if the click noise (3) influences the system application. the timing example is shown in this figure. (5) dzf pins are ?l? in the power-down mode (rstb pin = ?l?). figure 9. power-down/up sequence example
[AK4388A] ms1008-e-02 2010/09 - 13 - reset function (mclk, lrck or bick stop) when the mclk, lrck or bick stops, the digital circuit of the AK4388A is placed in power-down mode. when the mclk, lrck and bick are restarted, power-down mode is released and the AK4388A returns to normal operation mode. normal operation internal state digital circuit power-down normal operation gd gd d/a out (analog) d/a in (digital) clock in mclk, bick, lrck (1) (2) external mute (5) (1) mclk stop rstn pin power-down power-down (3) (3) (3) vcom (5) clock in mclk, bick, lrck external mute (5) lrck stop (5) (5) clock in mclk, bick, lrck external mute (5) bick stop (5) (5) (4) notes. (1) the analog output corresponding to a specific digital input has group delay (gd). (2) digital data can be stopped. the click noise, after mclk, lrck and bick are input again, can be reduced by inputting the ?0? data during this period. (3) click noise occurs within 20usec or 20usec +3 ~ 4lrck from the riding edge (? ?) of the rstn pin or mclk inputs. click noise also occurs within 20usec when mclk, lrck or bick is stopped. (4) the analog output becomes idle voltage when mclk is stopped. it becomes vcom voltage if lrck or bick is stopped when mclk is input. (5) mute the analog output externally if click noise (3) adversely affect system performance. figure 10. clock stop sequence
[AK4388A] ms1008-e-02 2010/09 - 14 - system design figure 11 shows the system connection diagram. an evaluation board (akd4388a) is available for fast evaluation as well as suggestions for peripheral circuitry. mclk 1 bick 2 sdti 3 lrck 4 rstn 5 smute 6 a cks 7 dif0 8 dzf 16 dem 15 vdd 14 vss 13 vcom 12 aoutl 11 aoutr 10 dif1 9 master clock AK4388A fs 24bit audio data reset & power down 64fs 10u 0.1u + rch out lch out analog ground digital ground a nalog supply 5v + 10u optional external mute circuits mode setting figure 11. typical connection diagram notes: - lrck = fs, bick=64fs. - when aout drives capacitive load, a resistor must be connected in series between aout and capacitive load. - all input pins except dif1 and dem pins must not be left floating.
[AK4388A] ms1008-e-02 2010/09 - 15 - 1. grounding and power supply decoupling vdd and vss are supplied from analog supply and must be sepa rated from system digital supply. decoupling capacitor, especially 0.1 f ceramic capacitor, for high frequency should be placed as near to vdd as possible. the differential voltage between vdd and vss pins set the analog output range. 2. analog outputs the analog outputs are single-ended and centered on the vcom voltage. the output signal range is typically 3.20vpp (typ@vdd=5v). the internal switched-cap acitor filter and continuous-time filter a ttenuate the noise generated by the delta-sigma modulator beyond the audio passband. the output voltage is a positive full scale for 7fffffh (@24bit) and a negative full scale for 800000h (@24bit). the ideal output is vcom voltage for 000000h (@24bit). the analog outputs have dc offsets of vcom + a few mv. this dc offsets on analog outputs are eliminated by ac coupling. figure 12 shows an example of the external lpf with 3.20vpp (1.13vrms) output. figure 13 shows an example of the external lpf with 2vrms output. aout 10u 220 2.2nf AK4388A 22k 3.2vpp (1.13vrms) analog out fc=328.8khz, g=-0.064db at 40khz figure 12. external 1 st order lpf circuit example (simple) 390p 3.9k 2.7k 3.9k 390p +vop 3.3k -vop aout 10u fc=125.8khz, q=0.752, g=0.058db at 40khz analog out 22k AK4388A 5.93vpp (2.09vrms) figure 13. external 2 nd order lpf circuit example (using op-amp with dual power supplies)
[AK4388A] ms1008-e-02 2010/09 - 16 - package 0-10 detail a seating plane 0.10 0.17 0.05 0.22 0.1 0.65 *5.0 0.1 1.1 (max) a 1 8 9 16 16pin tssop (unit: mm) *4.4 0.1 6.4 0.2 0.5 0.2 0.1 0.1 note: dimension "*" does not include mold flash. 0.13 m package & lead frame material package molding compound: epoxy lead frame material: cu lead frame surface treatme nt: solder (pb free) plate
[AK4388A] ms1008-e-02 2010/09 - 17 - marking (AK4388Aet) akm 4388aet xxyyy 1) pin #1 indication 2) date code : xxyyy (5 digits) xx: lot# yyy: date code 3) marketing code : 4388aet 4) asahi kasei logo revision history date (yy/mm/dd) revision reason page contents 08/09/19 00 first edition 08/10/17 01 description addition 10 de-emphasis filter ?in case of double speed and quad speed mode, the digital de-emphasis filter is always off.? was added. 10/09/28 02 specification change 16 package the package dimension was changed.
[AK4388A] ms1008-e-02 2010/09 - 18 - important notice z these products and their specifications are subject to change without notice. when you consider any use or application of these produc ts, please make inquiries the sales office of asahi kasei microdevices corporation (akm) or authorized distributors as to current status of the products. z descriptions of external circuits, application circuits, software and other related information contained in this document are provided only to illustrate the operation and application exampl es of the semiconductor products. you are fully responsible for the incorporation of these external circuits, application circuits, software and other related information in the design of your e quipments. akm assumes no responsibility fo r any losses incurred by you or third parties arising from the use of these information herein. akm assumes no liability for infringement of any patent, intellectual property, or other rights in the applica tion or use of such information contained herein. z any export of these products, or devices or systems containi ng them, may require an export license or other official approval under the law and regulations of the country of e xport pertaining to customs and tariffs, currency exchange, or strategic materials. z akm products are neither intended nor aut horized for use as critical components note1 ) in any safety, life support, or other hazard related device or system note2 ) , and akm assumes no responsibility fo r such use, except for the use approved with the express written consent by representative director of akm. as used here: note1 ) a critical component is one whose failure to functi on or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. note2 ) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aeros pace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z it is the responsibility of the buyer or distributor of akm products , who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above conten t and conditions, and the buyer or distributor agrees to assume any and all responsib ility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.

▲Up To Search▲

Price & Availability of AK4388A

	To Download AK4388A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .